1. Field of the Invention
The present invention relates to memory devices. In particular, one embodiment of the present invention relates to a structure of a memory cell for retaining data.
2. Description of the Related Art
A memory device utilizing semiconductor characteristics (hereinafter just referred to as a memory device) has been equipped for a variety of electronic devices and put into many products. Memory devices can be roughly classified into a volatile memory and a nonvolatile memory. The volatile memory includes in its category a register, an SRAM (static random access memory), and a DRAM (dynamic random access memory); the nonvolatile memory includes in its category a Flash EEPROM (flash memory).
The SRAM, which retains stored data with a circuit such as a flip flop, involves a large number of elements per memory cell (for example, six transistors per memory cell), increasing the cost per storage capacity.
On the other hand, the DRAM has a simple structure where each memory cell consists of a transistor and a capacitor. Therefore, as compared to the other volatile memories, the number of semiconductor elements included in each memory cell is less, so that the storage capacity per unit area can be increased and the cost can be reduced. However, in the DRAM, data is lost in reading stored data, and electric charge is leaked from the transistor as time passes, whereby stored data is lost; thus, a refresh operation needs to be repeated several tens of times per second. The repeat of the refresh operation leads to an increase in power consumption.
Patent Document 1 discloses a structure of a DRAM where a volatile memory and a nonvolatile memory are combined so that a refresh operation does not need to be performed.